The silicon bipolar transistor has been the device of choice for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm.sup.2 and support relatively high blocking voltages in the range of 500-1000 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias signal. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion-layer is formed in the P-type active (or channel) region in response to the application of a positive gate bias signal. The inversion-layer electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET's gate electrode is separated from the active (or channel) region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the active (or channel) region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's active (or channel) region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented.
Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as "second breakdown". Power MOSFETs can also easily be paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
In view of these desirable characteristics, many variations of power MOSFETs have been designed. Two popular types are the double-diffused MOS (DMOS) device and the ultra-low on-resistance MOS device (UMOS). The DMOS structure and its operation and fabrication are described in the textbook by coinventor Baliga entitled Modern Power Devices, the disclosure of which is hereby incorporated herein by reference. Chapter 6 of this textbook describes power MOSFETs at pages 263-343. FIG. 1 herein is a reproduction of FIG. 6.1(a) from the above cited textbook, and illustrates a cross-sectional view of a basic DMOS structure. The DMOS structure is fabricated using planar diffusion technology.
The UMOS device, also referred to as a "Trench DMOS" device, is described in publications entitled: An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process, by Ueda et al., IEEE Transactions on Electron Devices, Vol. ED34, No. 4, April (1987), pp. 926-930; Numerical and Experimental Comparison of 60V Vertical Double-Diffused MOSFETS and MOSFETS with a Trench-Gate Structure by Chang, Solid State Electronics, Vol. 32, No. 3, pp. 247-251 (1989); Trench DMOS Transistor Technology for High-Current (100A Range) Switching by Bulucea et al., Solid State Electronics, Vol. 34, No. 5, pp. 493-507 (1991); and Extended Trench-Gate Power UMOSFET Structure with Ultralow Specific On-Resistance, by Syau et al., Electronics Letters, Vol. 28, No. 9, pp. 865-867 (1992). FIG. 2 herein is a reproduction of a portion of FIG. 1 of the above identified Ueda et al. publication illustrating an embodiment of the UMOS structure.
A third example of a silicon power MOSFET is shown in FIG. 3. FIG. 3 is a reproduction of FIG. 4 from U.S. Pat. No. 4,903,189 to Ngo et al. and coinventor Baliga, the disclosure of which is hereby incorporated herein by reference. This MOSFET 170, which includes trenches 178 at a face thereof and contains no P-N junctions, is commonly referred to as an accumulation-mode FET ("ACCU-FET") because turn-on is achieved by forming a conductive accumulation layer between the FET's source 186 and drain 182 regions. FIG. 3 shows a plurality of parallel connected ACCU-FET cells, each defined by mesas 179 and opposing trenches 178.
A fourth example of a vertical power MOSFET is shown in FIG. 4A. FIG. 4A is a reproduction of FIG. 3 from U.S. Pat. No. 5,168,331 to H. Yilmaz. In particular, this MOSFET includes a "free floating" shield region 30 (P or N-) which serves as a buffer to reduce the strength of the electric field at point 18, which is adjacent to a corner in the profile of the gate 12.
The above-described beneficial characteristics of power MOSFETs are typically offset, however, by the relatively high on-resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, a MOSFET's operating forward current density is typically limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. One example of a hybrid device is the Insulated Gate Bipolar Transistor (IGBT), disclosed in section 7.2 of the aforementioned Baliga textbook.
The IGBT combines the high impedance gate of the power MOSFET with the small on-state conduction losses of the power bipolar transistor. An added feature of the IGBT is its ability to block both forward and reverse bias voltages. Because of these features, the IGBT has been used extensively in inductive switching circuits, such as those required for motor control applications. These applications require devices having wide forward-biased safe-operating-area (FBSOA) and wide reverse-biased safe-operating-area (RBSOA).
One embodiment of an IGBT is disclosed in an article by coinventor B. J. Baliga and M. S. Adler, R. P. Love, P. V. Gray and N. Zommer, entitled The Insulated Gate Transistor: A New Three terminal MOS Controlled Bipolar Power Device, IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), the disclosure of which is hereby incorporated herein by reference. Based on experimental results, on-state losses were shown to be greatly reduced when compared to power MOSFETs. This was caused by the conductivity modulation of the IGBT's drift region during the on-state. Moreover, very high conduction current densities in the range of 200-300 A/cm.sup.2 were also achieved. Accordingly, an IGBT can be expected to have a conduction current density approximately 20 times that of a power MOSFET and five (5) times that of an equivalent bipolar transistor. Typical turn-off times for the IGBT can be in the range of 10-50 .mu.s.
The basic structure of the IGBT is shown in cross-section in FIG. 5A, which is a reproduction of FIG. 1 from the aforementioned Baliga et al. article. In the IGBT, forward conduction can occur by positively biasing the anode (or electron "collector") with respect to the cathode (or electron "emitter") and applying a positive gate bias signal of sufficient magnitude to invert the surface of the P-base region under the gate. By creating an inversion-layer in the P-base region, electrons are allowed to flow from the N+ emitter region to the N-base region. In this forward conducting state, the junction J2 is forward biased and the P+ anode region injects holes into the N-Base region. As the anode bias is increased, the injected hole concentration increases until it exceeds the background doping level of the N-base. In this regime of operation, the device operates like a forward-biased P-i-N diode with heavy conductivity modulation of the N-base region. In the reverse bias region, the anode is biased negative with respect to the cathode and the lower junction (J3) is reversed biased, thereby preventing conduction from the cathode to anode even though the upper junction (J2) is forward biased. This provides the device with its reverse blocking capability.
Another IGBT which includes a "free floating" shield region for improving the reverse blocking capability is shown in FIG. 4B, which is a reproduction of FIG. 10 from the aforementioned '331 patent to Yilmaz. In particular, this IGBT includes a "free floating" shield region 85 (P or N-) which serves as a buffer to reduce the strength of the electric field at point 87, which is adjacent to a corner in the profile of the gate 82.
The IGBT can typically operate at high current densities even when designed for operation at high blocking voltages. As long as the gate bias is sufficiently large to produce enough inversion-layer charge for providing electrons into the N-base region, the IGBT forward conduction characteristics will look like those of a P-i-N diode. However, if the inversion-layer conductivity is low, a significant voltage drop will begin to appear across this region like that observed in conventional MOSFETs. At this point, the forward current will saturate and the device will operate in its active or current saturation region, as shown in FIG. 5B, which is a reproduction of FIG. 2 from the aforementioned Baliga et al. article. As will be understood by those skilled in the art, high voltage current saturation is ultimately limited by avalanche induced breakdown. Finally, because the elimination of the inversion-layer cuts off the supply of electrons into the N-base region and because there is no self-sustaining source of electrons to the N-base region, the IGBT will typically turn off even if the anode remains positively biased.
It is recognized that although gate-controlled bipolar transistors, such as the IGBT, represent a significant improvement over using bipolar or MOSFET devices alone, even lower conduction losses can be expected by using a thyristor. This is because thyristors offer a higher degree of conductivity modulation and a lower forward voltage drop when turned on. Consequently, the investigation of thyristors is of great interest so long as adequate methods for providing forced gate turn-off can also be developed. As will be understood by one skilled in the art, a thyristor in its simplest form comprises a four-layer P1-N1-P2-N2 device with three P-N junctions in series: J1, J2, and J3, respectively. The four layers correspond to the anode (P1), the first base region (N1), the second base or P-base region (P2) and the cathode (N2), respectively. In the forward blocking state, the anode is biased positive with respect to the cathode and junctions J1 and J3 are forward biased and J2 is reversed-biased. Most of the forward voltage drop occurs across the central junction J2. In the forward conducting state, all three junctions are forward biased and the voltage drop across the device is very low and approximately equal to the voltage drop across a single forward biased P-N junction.
An inherent limitation to the use of thyristors for high current applications is sustained latch-up, however, arising from the cross-coupled P1-N1-P2 and N1-P2-N2 bipolar transistors which make up the four layers of the thyristor. This is because sustained thyristor latch-up can result in catastrophic device failure if the latched-up current is not otherwise sufficiently controlled by external circuitry or by reversing the anode potential. Sustained latch-up can occur, for example, when the summation of the current gains for the thyristor's cross-coupled P1-N1-P2 and wide base P1-N2-P2 transistors (.alpha..sub.pnp, .alpha..sub.npn) exceeds unity. When this occurs, each transistor drives the other into saturation and provides the other with a self-sustaining (i.e., regenerative) supply of carriers to the respective transistor's base region. An alternative to providing external circuitry or reversing the anode potential to obtain turn-off, however, is to use a MOS-gate for controlling turn-on and turn-off.
Several methods for obtaining MOS-gated control over thyristor action, including sustained latch-up, exist. For example, in the MOS-controlled thyristor (MCT), turn-off is provided by shorting the emitter-base junction of the N-P-N transistor to thereby produce a reduction in gain. This form of control ideally raises the holding current of the thyristor to a level above the operating current level. An MCT structure has been reported which utilizes a P-channel MOSFET integrated into the cathode region of a thyristor for turn-off control, and an N-channel MOSFET integrated into the P-base region for turn-on control. This device and its complementary counterpart are described in an article by V. A. K. Temple, entitled "MOS Controlled Thyristors (MCT's)," published in IEDM Technology Digest, Abstract 10.7, pp. 282-285, (1984). However, the maximum controllable current density, which is a direct measure of a device's ability to turn-off, is limited by the MOSFET inversion-layer channel resistance and other resistances in the base region. Because of the lower mobility of holes in silicon, MCT's built from n-type high-voltage drift layers exhibit relatively poor current turn-off characteristics.
An example of a MOS-gated thyristor which overcame many of the drawbacks associated with the MCT is the depletion-mode thyristor (DMT). This device is described in an article by coinventor B. J. Baliga and H. Chang, entitled "The MOS Depletion-Mode Thyristor: A New MOS-Controlled Bipolar Power Device," published in IEEE Electron Device Letters, Vol. 9, No. 8, August (1988). In the DMT, a depletion-mode MOSFET is placed in series with the base one of the coupled transistors (i.e., P.sup.+ -N.sup.+ N-P transistor). Accordingly, once the thyristor is turned-on, current flow can be interrupted by the application of a negative gate bias signal to the depletion-mode MOSFET. This is because the application of a negative gate bias signal causes the MOSFET to switch off and causes the base drive current to the P.sup.+ -N.sup.+ N-P coupled transistor to be pinched off.
Recently, a base resistance controlled thyristor (BRT) was described in U.S. Pat. No. 5,099,300, by coinventor B. J. Baliga, issued Mar. 24, 1992, and in an article entitled "A New MOS-Gated Power Thyristor Structure with Turn-Off Achieved by Controlling the Base Resistance," by M. Nandakumar, coinventors B. J. Baliga, M. S. Shekar, and S. Tandon and A. Reisman, IEEE Electron Device Letters, Vol. 12, No. 5, pp. 227-229, May, 1991, both of which are hereby incorporated herein by reference. The BRT operates by modulating the lateral P-base resistance of the thyristor using MOS gate control. The BRT can be turned-off by the application of a negative gate bias signal to a P-channel enhancement-mode MOSFET to thereby reduce the resistance of the P-base by shunting majority charge carriers to the cathode. As will be understood by one skilled in the art, the reduction in P-base resistance causes an increase in the device's holding current to above the operational current level and shuts-off the device.
A BRT with both single-polarity and dual-polarity turn-on and turn-off control is also described in U.S. Pat. No. 5,198,687, to coinventor B. J. Baliga, issued Mar. 30, 1993, the disclosure of which is hereby incorporated herein by reference. In this BRT, a depletion-mode MOSFET is provided for electrically connecting the second base region to a diverter region. The depletion-mode MOSFET turns the thyristor off by shunting current from the second base region to the cathode region, via the diverter region, in response to an appropriate polarity bias signal.
In another device, described in an article entitled "The MOS-Gated Emitter Switched Thyristor," by coinventor B. J. Baliga, published in IEEE Electron Device Letters, Vol. 11, No. 2, pp. 75-77, February, 1990, turn-on is achieved by forcing the thyristor current to flow through an N-channel enhancement-mode MOSFET and floating N.sup.+ emitter integrated within the P-base region. This article is hereby incorporated herein by reference. A cross-sectional representation of this structure and equivalent circuit is shown in FIGS. 6A and 6B, which are reproductions of FIG. 1 from the aforesaid Baliga article. Because the N.sup.+ emitter is electrically isolated from the cathode contact, it is commonly referred to as a "floating emitter" region. Accordingly, as used herein, a "floating emitter" is an emitter region which does not make direct electrical contact to the cathode contact.
As will be understood by one skilled in the art, the length of the floating N.sup.+ emitter region, which determines the value of large resistance R shown in FIG. 6B, controls the holding current and triggering current levels for the device. Turn-off of the emitter switched device (EST) is accomplished by reducing the gate voltage on the MOSFET to below the threshold voltage. This cuts off the floating N.sup.+ emitter region from the cathode and ideally shuts the device off.
Unfortunately, the integration of the MOSFET into the P-base region causes a parasitic thyristor to be formed, as shown in FIG. 6A, wherein the N.sup.+ source region of the N-channel MOSFET also comprises the N.sup.+ emitter of the vertical parasitic thyristor between the anode and cathode. If this thyristor turns-on, the EST can no longer be turned off by reducing the MOSFET gate voltage to zero. Turn-on of the parasitic thyristor is initiated by the onset of electron injection from the N.sup.+ emitter region when forward biased and is dictated by the resistance of the P-base under the N.sup.+ emitter region.
The likelihood that parasitic latch-up will occur can be reduced if the P-base resistance (small R) is lowered by making the length of the N.sup.+ emitter region small and by using a P+ diffusion to reduce the sheet resistance of the P-base. By keeping the resistance under the N.sup.+ emitter of the parasitic thyristor as small as possible, the probability that the P.sup.+ /N.sup.+ junction will become forward biased when the thyristor is turned-on is reduced. The likelihood of injection of electrons from the N.sup.+ emitter can also be reduced by shorting the P.sup.+ diffusion to the cathode, as shown. These techniques can also be used to reduce the likelihood of parasitic latch-up in an EST which has a dual-channel lateral MOSFET. This EST is described in an article entitled "High-Voltage Current Saturation in Emitter Switched Thyristors," by coinventors M. S. Shekar and B. J. Baliga, and M. Nandakumar, S. Tandon and A. Reisman, published in IEEE Electron Device Letters, Vol. 12, No. 7, pp. 387-389, July (1991), the disclosure of which is hereby incorporated herein by reference.
Other attempts to limit the likelihood of sustained parasitic latch-up have been made. For example, in U.S. Pat. No. 5,294,816 entitled Unit Cell Arrangement for Emitter Switched Thyristor with Base Resistance Control, issued Mar. 15, 1994, to coinventor M.S. Shekar, M. Nandakumar and coinventor B. J. Baliga, the probability of sustained parasitic thyristor action preventing turn-off was reduced by incorporating a current diverting means adjacent the parasitic thyristor to thereby reduce the effective resistance of the second base region during turn-off and further inhibit latch-up by preventing the forward biasing of the P.sup.+ /N.sup.+ junction beneath the cathode. However, this EST includes a lateral MOSFET which can produce an additional 0.4-0.5 Volt drop across the thyristor for forward current densities in the range of 250 A/cm.sup.2. Further, to obtain reasonable values for the latching and holding currents, the N.sup.+ floating emitter length is typically large, thereby increasing the lateral dimensions of the EST and increasing the cell pitch.
In U.S. Pat. No. 5,306,930 entitled Emitter Switched Thyristor with Buried Dielectric Layer, issued Apr. 26, 1994 to coinventor B. J. Baliga, the formation of a parasitic thyristor was inhibited by incorporating a buried dielectric layer, such as silicon dioxide (SiO.sub.2), between the cathode region and the second base region. The insulating region was preferably formed using a conventional SIMOX technique.
In U.S. Pat. No. 5,293,054 entitled Emitter Switched Thyristor Without Parasitic Thyristor Latch-Up Susceptibility, issued Mar. 8, 1994, to coinventors M. S. Shekar and B. J. Baliga, parasitic latch-up was prevented using a lateral transistor having an active region in the first base region and a metal strap on the surface of the substrate, between the lateral transistor and the thyristor's floating emitter region.
Another example of a MOS-gated thyristor which includes a trench is disclosed in U.S. Pat. No. 5,202,750 to Gough. In particular, FIG. 7, which is a reproduction of FIG. 1 from the '750 patent, illustrates a semiconductor device having a thyristor formed by regions 4,5,8 and 9.
Notwithstanding these attempts at limiting the susceptibility of thyristors and particularly ESTs to sustained parasitic thyristor latch-up, the presence of either a current diverting means and/or insulating region between the cathode region and the second base region may increase the overall dimensions of the EST and the complexity of the fabrication process. Accordingly, an EST having reduced lateral dimensions and capable of being formed by a simplified fabrication process is desired for applications requiring low forward voltage drop, high maximum controllable current density and MOS-gated turn-on and turn-off control. It is further desirable to form an EST without a parasitic thyristor therein.